1. Field of the Invention
The present invention relates to a simulation method for estimating I-V characteristic change due to transistor degradation, such as hot carrier and NBTI (Negative Bias Temperature Instability), an information processing apparatus, and a program to be executed by a computer.
2. Description of Related Art
Hot carrier and NBTI are known as phenomena which decrease the reliability of a MOSFET. The hot carrier dominantly influences characteristic degradation of an NMOSFET, and the NBTI dominantly influences characteristic degradation of a PMOSFET. The influence by these phenomena appears in the relationship between a decrease in drain current flowing between a source electrode and a drain electrode by injection of charge into gate oxide, and voltage application time.
When high voltage is applied to drain voltage Vds and the intermediate potential of Vds is applied to gate voltage Vgs, the influence of hot carrier to the NMOSFET become larger as gate length Lg becomes shorter. When high voltage is applied to Vgs, NBTI on the PMOSFET occurs at any Vds and with any Lg. It is also said that these phenomena are influenced by back bias voltage Vbs. The back bias voltage is voltage applied to a substrate on which a transistor is formed. If the transistor is formed in a well diffusion layer, the back bias voltage is voltage applied to the well diffusion layer.
Drain current is used as a value for evaluating transistor degradation. Drain current Ids is measured under the conditions of Vgs=Vcc and Vds=Vcc/2. The rate of change in the drain current is defined by a formula of ΔIds/Ids0=(Ids (initial state)−Ids (after degradation)/Ids (initial state). Ids0 indicates Ids in the initial state at the time when voltage application starts. Transistor lifetime τ is defined as time required until ΔIds/Ids0=10% is satisfied after start of voltage application. It is assumed that 10% is a reference degradation rate.
FIG. 1 shows an example of a graph for determining the lifetime of a transistor based on actual measurements. The vertical axis in FIG. 1 indicates the degradation rate and the horizontal axis indicates time. A method for measuring the characteristic shown in FIG. 1 will be described below.
Gate voltage VGS is set for one voltage selected from within a predetermined range of Vcc, and Vcc/2 is set for drain voltage VDS. Drain current ID is measured at predetermined time intervals. In FIG. 1, values obtained by dividing the amount of change in the drain current by the drain current at the time of start of voltage application are plotted, and the plotted points are connected by a line. Similarly, measurement is performed for each of multiple kinds of Vcc's in a similar manner. The graph shown in FIG. 1 is obtained by plotting measurement points for each selected Vcc and connecting the plotted points.
In the graph shown in FIG. 1, attention is paid to the measurement condition of Vgs=Vgs1, and the time when the degradation rate is 10% is indicated by an arrow. In this way, the transistor lifetime τ is determined based upon actually measured data. By applying the result to the formula of Deg=f (Vgs, Vds, Lg, t), a degradation model parameter is determined.
FIGS. 2A and 2B are graphs showing transistor characteristics obtained from the measurement result in FIG. 1. FIG. 2A shows the relationship between the transistor lifetime and the reciprocal of the drain voltage, and FIG. 2B shows the relationship between the transistor lifetime and the gate voltage.
As shown in FIG. 2A, the relationship between the transistor lifetime τ and the reciprocal of the drain voltage (1/Vds) is shown as a straight line rising from left to right. From this graph, it is seen that the transistor lifetime τ becomes longer as 1/Vds becomes larger, and the transistor lifetime τ becomes shorter as Vds becomes larger. By determining the value of Vds from this straight line, it is possible to estimate τ at that time.
In the graph shown in FIG. 2B, a quartic function is obtained by plotting τ for each Vgs and connecting the plotted points. As shown in the graph in FIG. 2B, it is possible to model the transistor degradation phenomena based on the measurement result in FIG. 1.
Since it is possible to estimate transistor degradation from the measurement result in FIG. 1, reliability simulation is performed in which the measurement result is inputted to a computer to estimate the transistor degradation phenomena and predict a circuit operation.
The reliability simulation will be simply described. The reliability simulation includes degradation simulation for estimating the degradation of the lifetime of a transistor during the time when the transistor is being used, and circuit simulation for predicting a circuit operation using the result of the degradation simulation.
First, by performing degradation simulation for substituting a degradation model parameter that is determined based on the measurement result, into the degradation model formula, device degradation information during the time when the transistor is being used, is outputted. Next, by adding a stress I-V model parameter to the device degradation information and by performing circuit simulation using a transistor model parameter after degradation, a circuit waveform after degradation is obtained. An example of these simulations is disclosed in Japanese Patent Laid-Open No. 2003-188184.
The transistor model parameter is based on a particular transistor model, such as BSIM, which is required for ordinary circuit simulation. BSIM is a transistor model developed at a university in U.S., and it is widely utilized as a standard model.
An example of device degradation information outputted from degradation simulation will be described. FIG. 3 is a graph showing an example of measurements of the drain current of the transistor and a simulation result.
In the graph in FIG. 3, an initial state, a 50%-degradation state and an 80%-degradation state are shown, in terms of the Ids-Vds dependence. The plotted points in the graph indicate measurement results, and the lines drawn along the plotted points indicate simulation values. From FIG. 3, it is seen that the measurement values and the simulation values almost agree with each other, and that the evaluation target transistor is compatible with the degradation model formula of the simulation.
However, as the gate length of transistors becomes shorter in response to the demand for further miniaturization of semiconductor integrated circuits, the degradation phenomena of the transistors gradually become incompatible with the degradation model formulas of the existing degradation lifetime simulations. If the degradation phenomena of a transistor do not match a degradation model formula, the result of the simulation will not correspond to actual electrical characteristics.
For example, in the case of a model in which the degradation model formula is such that the τ-Vgs dependence is applied to a quartic function, the degradation model formula is compatible with a transistor that shows the τ-Vgs dependence of the graph in FIG. 2B. However, the degradation model formula is not compatible with a transistor that shows τ-Vgs dependence that is different from a quartic function, such as a quintic function, a sextic function and the like.
Even in the case of a model obtained by adapting a particular transistor model, such as BSIM, to be compatible with all of various kinds of transistors, since a degradation model formula and the particular transistor model are closely associated with each other in the existing degradation lifetime simulation, the existing degradation lifetime simulation is limited to transistors compatible with the degradation model formula, and it is difficult for the existing degradation lifetime simulation to be compatible with transistors that are incompatible with the degradation formula.